Y Explorations, Inc.

eXCite

ANSI-C to RTL automatically

eXCite takes ISO/ANSI-C and synthesizes it to Verilog or VHDL RTL suitable for input to FPGA or ASIC logic synthesis tools.

Automatic Bus Protocol Insertion

Diagram

Perhaps the most important task in preparing your C code for synthesis is to identify and insert channels which specify how the generated hardware block will communicate with its surroundings.

Channels can be streaming, blocking, or even indexed, like arrays.

Channels are read and/or written with simple C procedure calls which you add to the C code or are added for you by specifying pragmas.

eXCite takes these channels and based on your hardware platform, automatically figures out how to interface to platform buses.

For example, if you're using an Altera platform with Avalon interfaces, your channels will be automatically mapped and synthesized to Avalon Streaming and Memory Mapped Interfaces. You don't need to know how those interfaces work at all. You will need to know how to connect the resulting hardware block to the platform, however, which is easily done with Altera's SOPC Builder (www.altera.com).

Automatic Verification

One of the hardest tasks in designing hardware is verifying its correctness. With the eXCite design flow, you verify the C behavior first and after synthesis is complete, a VHDL or Verilog testbench is generated automatically for you. This testbench can then be used with any RTL simulation tool to verify the same inputs and outputs that were tested on the C behavior.

Automatic IP Reuse

A key approach to good hardware design is using and reusing previous hardware designs.

eXCite will automatically use IPs to synthesize a C program wherever the behavior can be implemented by that IP. For example, floating point operations can be automatically mapped to Altera's pipelined floating point megafunctions. Support for many of the math.h functions, such as sqrt(), cos(), sin() are available in the IP Template library.

Many other features

  • Pipelining. eXCite pipelines loops or treats an entire design as a pipeline, automatically inserting registers and scheduling pipelined IP for optimal throughput.
  • Bit reduction. eXCite will automatically reduce bitwidths of datatypes when possible. The user may also use pragmas to specify the width of datatypes if it is known that the default size of the C datatype is too large.
  • Compiler optimizations eXCite performs compiler optimizations such as constant folding, partial evaluation, algebraic elimination, common subexpression elimination and more.

Specifications

Input: ISO/ANSI C. eXCite supports a substantial subset of ISO/ANSI C. Pointers, struct, type definitions are all supported, for example.

Output: VHDL, Verilog, and SystemC. eXCite outputs an RTL model of VHDL, Verilog or SystemC generally in two-process form having a sequential and combinational process.

Libraries: Altera, Xilinx, Actel. eXCite has built-in data for devices from Altera, Xilinx and Actel. A technology library generator is also available to customize ASIC library information.

Platform support: Altera Avalon. eXCite has direct support for Altera's Avalon interface. Other platforms can be easily customized with eXCite's Virtual Platform which includes standard memory, handshake, and streaming interfaces.

Product Configurations: eXCite comes in the full Professional version or in a slightly more limited, but cheaper FPGA version.

Licensing: Floating and Node-locked licenses are supported.

Etymology: eXCite gets its name and peculiar capitalization from YXI's first synthesis product XC, the eXplorations Compiler, offered in 1998 as part of the eXplorations Tool Suite. XC was the first product to combine behavior synthesis with automatic design reuse.

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