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RTL output from eXCite is ready for logic simulation using Active-HDL, Riviera-Pro, and HES.
RTL output from eXCite is ready for logic synthesis using ALTERA Quaruts II. eXCite can also generate RTL HDL composed of Altera MegaFunctions (tm).
RTL output from eXCite is ready for logic synthesis using XILINX ISE.




