Partners and Alliances
Partners
RTL output from eXCite is ready for logic simulation using Active-HDL, Riviera-Pro, and HES.
RTL output from eXCite is ready for logic synthesis using ALTERA Quaruts II. eXCite can also generate RTL HDL composed of Altera MegaFunctions (tm).
RTL output from eXCite is ready for logic synthesis using XILINX ISE.
Collaborative research on System-level C descriptions (Hy-C)
eXCite comes bundled with Omron's "Frantio" FPGA platform.
eXCite comes bundled with Hitachi's "LogicBench" FPGA platform.
Educational Institutes
Tsinghua University Beijing is the top-rated university in China. Faculty from the Department of Electronics Engineering and Y Explorations are collaborating on research and teaching efforts using C-to-FPGA synthesis technology.
- Collaborative design of the FIR Filter Based Hardware and Software (2011)
- Acceleration of Pedestrian Detection Algorithm on Novel C2RTL HW/SW Co-design Platform (ICGCS 2010)
- HW/SW Co-Design and Research for Mid-High Speed Data Processing Chips in Wireless Sensor Network (2010)
- Chapter "A Hierarchical C2RTL Framework for Rapid Design of Embedded Systems" in Book "Embedded System", ISBN 979-953-307-580-7 (To be published)
- Used as C2RTL tools in China State 863 project "Low Power and Computation Design for Muilt-Core SOC in On-Chip Sensor Network" (2009-2010)
Nagoya University is a top-ranked Japanese National University located in Chikusa-ku, Nagoya, Japan. Faculty from the School of Information Science and Y Explorations have collaborated since 2003 on a variety of ESL research projects.
- A case study on MPEG4 decoder design with SystemBuilder (VLSI-DAT 2009)
- Automatic instrumentation of profilers for FPGA-based design space exploration (FPT 2009)
- CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis (ISCAS 2008)
- Behavioral Partitioning with Exploiting Function-Level Parallelism (ISOCC 2008)













