Y Explorations, Inc.

Partners and Alliances

Partners

Aldec

RTL output from eXCite is ready for logic simulation using Active-HDL, Riviera-Pro, and HES.


Aldec

RTL output from eXCite is ready for logic synthesis using ALTERA Quaruts II. eXCite can also generate RTL HDL composed of Altera MegaFunctions (tm).


Xilinx

RTL output from eXCite is ready for logic synthesis using XILINX ISE.